1. Field of the Invention
The present invention relates to non-volatile memory devices and, more particularly, to non-volatile memory devices having two bits per cell.
2. Description of Related Art
A non-volatile semiconductor memory device is designed to maintain programmed information even in the absence of provided power. The read-only memory (ROM) is a non-volatile memory device commonly used in electronic equipment such as microprocessor-based digital electronic equipment and portable electronic devices such as cellular phones.
ROM devices are conventionally arranged into a plurality of memory cell arrays. Each memory cell includes a transistor, which typically comprises a metal-oxide-semiconductor field effect transistor (MOSFETs) that is juxtaposed between two intersecting bit lines and a word line. Data bit values or codes held by these memory cell transistors are permanently stored (until deliberate erasure) in the physical or electrical properties of the individual memory cells. Generally speaking, a consequence of the non-volatile nature of a ROM is that data stored in the memory device can only be read.
A relatively recent development in non volatile memory has been the advent of Nitride Read-Only Memory (NROM) devices. NROM devices offer a number of advantages over the 30 year old currently dominant floating gate devices such as EPROM, Flash, and EEPROM, which store charge in a conductive floating gate.
NROM cells can comprise 2 bit flash cells based on charge storage in an Oxide-Nitride-Oxide (ONO) dielectric. The NROM cell may comprise an n-channel MOSFET device wherein nitride is used as a trapping material between a top and bottom oxide. The ONO structure replaces the gate dielectric that is used in floating gate devices. The top and bottom oxide layers should be thicker than 50A to prevent any oxide damaging direct electron tunneling during programming.
NROM flash blocks may be added to standard CMOS processes by laying down the ONO layer after the field isolation but before the gate oxidation. Adding the NROM components typically has minimal effects on the CMOS thermal budgets. The NROM memory cells can be programmed by channel hot electron (CHE) injection, and erased by tunneling enhanced hot hole (TEHH) injection through the bottom oxide. The NROM cells operate as localized charge storage devices, which allows the trapped charge to remain only at the injection point. Thus, single bit failures commonly experienced by floating gate technologies may be reduced. This reduction may allow for further minimization of device size and increased device density without degradation in performance.
NROM devices can offer a number of significant advantages over floating gate devices. Both the bit size and the die size can be a factor of 3 or more smaller for NROM devices. NROM devices can also require 6 to 8 fewer photomask steps, their process complexity can be simpler, and it can be easier to integrate them with CMOS devices for embedded applications. Furthermore, NROM devices can be more suited to low voltage product implementation due to a lower erased threshold voltage. However, a common problem with NROM devices can be the lateral movement of holes and electrons between the two bits in NROM cells. Such lateral movement of holes and electrons (commonly known as cross-talk) can occur, especially after certain thermal processes.
The present invention relates to nonvolatile memory devices and methods of forming such nonvolatile memory devices. More particularly, the invention herein provides improved methods of manufacturing NROM memory devices. The improved processing methods may reduce the occurrence of electron movement and/or hole movement between bits in an NROM memory cell. Such electron and/or hole movement, otherwise known as cross-talk, can occur especially after certain thermal processes. In accordance with an aspect of the present invention, cutting the nitride layer of the ONO stack in each cell can attenuate or eliminate this problem of cross-talk between two bits of a memory cell. The invention provides a dielectric resolution enhancement coating technique to facilitate cutting of the nitride layer. The dielectric resolution enhancement coating technique can overcome photolithography limitations of patterning the ONO stack below dimensions around 0.15 xcexcm. Using a dielectric resolution enhancement coating technique in accordance with the present invention can allow for device dimensions which are smaller than the wavelength of the UV radiation used to pattern the photoresist and create the devices.
In accordance with an aspect of the present invention, a method for forming at least one nonvolatile memory device comprises providing a substrate with a trapping layer and photoresist features formed thereon; using the photoresist features as an implanting mask to form at least one bit line; forming a material layer between the photoresist features; removing the photoresist features; forming a polymer layer on surfaces of the material layer; and using the polymer layer as an etching mask to define the trapping layer.
In accordance with another aspect of the present invention, a method for forming a nonvolatile memory device can comprise forming a trapping layer on a prepared substrate; forming a patterned photoresist layer on the trapping layer; using the photoresist layer as an implanting mask to perform an implantation to form at least one bit line; forming a material layer on surfaces of the photoresist layer and trapping layer; planarizing the material layer to expose the photoresist layer; removing the photoresist layer; forming a polymer layer on surfaces of the material layer; using the polymer layer as an etching mask to pattern the trapping layer into at least one trapping layer strip; removing the material layer and the polymer layer; and forming at least one word line on the at least one trapping layer strip.
The trapping layer may comprise in sequence a first oxide layer, a nitride layer, and a second oxide layer, wherein the first oxide layer, the nitride layer, and the second oxide layer form an ONO stack. The ONO stack may be patterned such that the first oxide layer remains substantially unpatterned. The material layer may comprise a bottom anti-reflective coating (BARC) layer. The polymer layer that is formed on the material layer may be formed in an etcher. The step of planarizing the material layer may comprise an etch back process. The at least one bit line may comprise a plurality of bit lines, the at least one trapping layer strip may comprise a plurality of trapping layer strips, and the at least one word line may comprise a plurality of word lines.
In accordance with yet another aspect of the present invention, a method for forming a nonvolatile memory on a semiconductor substrate can comprise the steps of providing a prepared semiconductor substrate; forming a trapping layer on the semiconductor substrate; applying and patterning a photoresist over the trapping layer to form a plurality of photoresist strips; selectively implanting the semiconductor substrate to form a plurality of bit lines; forming a material layer on surfaces of the patterned photoresist and trapping layer; planarizing the material layer to expose the photoresist layer; removing the photoresist layer; forming a polymer layer on surfaces of the material layer; etching back portions of the trapping layer to form a plurality of trapping layer strips; removing the material layer and the polymer layer; and forming a plurality of word lines.
The implanting step can be followed by a step in which the trapping layer is patterned into a plurality of dual trapping layer strips. The trapping layer may comprise in sequence a first oxide layer, a nitride layer, and a second oxide layer, forming an ONO stack. The second oxide layer formed in the foregoing method may consume some portion of the nitride layer during its growth. The polymer layer can be formed using a dielectric resolution enhancement coating technique, which may be performed in an etcher. The polymer layer may be used as an etch mask to protect the underlying layers during etch processing.
In accordance with one aspect of the present invention, a nonvolatile memory device comprises a prepared semiconductor substrate in which a plurality of bit lines are implanted. The nonvolatile memory device comprises a plurality of trapping layer block structures, and a plurality of word lines positioned over corresponding members of the plurality of trapping layer block structures. The trapping layer block structures are separated from one another in the word line direction at locations between the bit lines. Each trapping layer block structure corresponds to a single bit in a memory cell. The plurality of trapping layer block structures may comprise an oxide layer and a nitride layer.
Any feature or combination of features described herein are included within the scope of the present invention provided that the features included in any such combination are not mutually inconsistent as will be apparent from the context, this specification, and the knowledge of one of ordinary skill in the art. Additional advantages and aspects of the present invention are apparent in the following detailed description and claims.